View QL4090-0PQ208C_2425681.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

6-55 90,000 usable pld gate quickram esp combining performance, density, and embedded ram ql4090 - quickram tm ql4090 rev g ql4090 - quickram device highlights high performance & high density 90,000 usable pld gates with 316 i/os 300 mhz 16-bit counters, 400 mhz datapaths, 160+ mhz fifos 0.35 m four-layer metal non-volatile cmos process for smallest die sizes high speed embedded sram 22 dual-port ram modules, organized in user-config- urable 1,152 bit blocks 5ns access times, each port independently accessible fast and effecient for fifo, ram, and rom functions easy to use / fast development cycles 100% routable with 100% utilization and complete pin-out stability variable-grain logic cells provide high performance and 100% utilization comprehensive design tools include high quality verilog/vhdl synthesis advanced i/o capabilities interfaces with both 3.3 volt and 5.0 bolt devices pci compliant with 3.3v and 5.0v busses for -1/-2/-3/-4 speed grades full jtag boundary scan registered i/o cells with individually controlled clocks and output enables d evice h ighlights figure 1. quickram block diagram architecture overview the quickram family of esps (embedded standard products) offers fpga logic in combination with dual- port sram modules. the ql4090 is a 90,000 usable pld gate member of the quickram family of esps. quickram esps are fabricated on a 0.35mm four-layer metal process using quicklogic?s patented vialink tm technology to provide a unique combina- tion of high performance, high density, low cost, and extreme ease-of-use. the ql4090 contains 1,584 logic cells and 22 dual port ram modules (see figure 1). each ram module has 1,152 ram bits, for a total of 25,344 bits. ram modules are dual port (one read port, one write port) and can be configured into one of four modes: 64 (deep) x18 (wide), 128x9, 256x4, or 512x2 (see fig- ure 2). with a maximum of 204 i/os, the ql4090 is available in 208-pqfp, 240-pin pqfp and 456-pin pbga packages. designers can cascade multiple ram modules to increase the depth or width allowed in single modules by connecting corresponding address lines together and dividing the words between modules (see figure 3). this approach allows up to 512-deep configura- tions as large as 16 bits wide in the smallest quick- ram device and 44 bits wide in the largest device. 22 ram blocks } 1,584 high spee d logic cells interface a rchitecture o verview
56 preliminary ql4090 - quickram tm 6-56 figure 2. quickram module software support for the complete quickram fam- ily, including the ql4016, is available through two basic packages. the turnkey quickworks tm pack- age provides the most complete esp software solu- tion from design entry to logic synthesis, to place and route, to simulation. the quicktools tm for worksta- tions package provides a solution for designers who use cadence, exemplar, mentor, syn-opsys, synplic- ity, viewlogic, veribest, or other third-party tools for design entry, synthesis, or simulation. the quicklogic variable grain logic cell features up to 16 simultaneous inputs and 5 outs within a cell that can be fragmented into 5 independent cells. each cell has a fan-in of 29 including register and control lines (see figure 4). figure 3. quickram module bits product summary product summary total of 316 i/o pins 308 bi-directional input/output pins, pci-compliant for 5.0 volt and 3.3 volt buses for -1/-2/-3/-4 speed grades 8 high-drive input/distributed network pins eight low-skew distributed networks two array clock/controlnetworks available to the logic cell flip-flop clock, set and reset inputs - each driven by and input-only pin six global clock/control networks available to the logic cell f1, clock, set and reset inputs and the input and i/o register clock, reset and enable inputs as well as the out- put enable control - each driven by an input-only or i/o pin, or any logic cell output or i/o cell feedback high performance input + logic cell + output total delays under 6 ns data path speeds over 400 mhz counter speeds over 300 mhz fifo speeds over 160+ mhz figure 4. logic cell wdata rdata rdata waddr wdata raddr ram module (1,152 bits) ram module (1,152 bits) p roduct s ummary qs a1 a2 a3 a4 a5 a6 os op b1 b2 c1 c2 ms d1 e1 np e2 d2 ns f1 f3 f5 f6 f2 f4 qc qr mp az oz qz nz fz
6-57 ql4090 - quickram tm 208 pin pqfp/cqfp pinout diagram 240 pin pqfp pinout diagram ql4090-1pq208c quickram pin #1 pin #53 pin #105 pin #157 ql4090-1pq240c quickram pin #121 pin #181 pin #61 pin #1
58 preliminary ql4090 - quickram tm 6-58 qfp 208/240 pinout table table 1: pqfp 208/240 pinout table 240 pqfp 208 pqfp function 240 pqfp 208 pqfp function 240 pqfp 208 pqfp function 240 pqfp 208 pqfp function 240 pqfp 208 pqfp function 1 208 i/o 51 43 gnd 98 84 i/o 145 125 i/o 194 168 i/o 2 1 i/o 52 44 i/o 99 85 i/o 146 126 i/o 195 169 i/o 3 2 i/o 53 45 i/o 100 86 i/o 147 127 gnd 196 nc i/o 4 3 i/o 54 46 i/o 101 87 i/o 148 128 i/o 197 170 i/o 5 4 i/o 55 47 i/o 102 88 i/o 149 nc i/o 198 171 i/o 6 5 i/o 56 48 i/o 103 89 i/o 150 129 glck/i 199 172 i/o 7 nc i/o 57 nc i/o 104 90 i/o 151 130 aclk/i 200 173 i/o 8 6 i/o 58 49 i/o 105 91 i/o 152 131 vcc 201 174 i/o 9 7 i/o 59 50 i/o 106 92 i/o 153 132 glck/i 202 175 i/o 10 8 i/o 60 51 i/o 107 nc i/o 154 133 glck/i 203 nc i/o 11 9 i/o nc 52 i/o 108 93 i/o 155 134 vcc 204 176 i/o 12 10 vcc nc 53 i/o 109 94 i/o 156 135 i/o 205 177 gnd 13 11 i/o 61 54 tdi 110 95 gnd 157 136 i/o 206 178 i/o 14 12 gnd 62 nc i/o nc 96 i/o 158 nc i/o 207 179 i/o 15 13 i/o 63 nc i/o 111 97 vcc 159 137 i/o 208 nc i/o 16 14 i/o 64 55 i/o nc 98 i/o 160 nc gnd 209 180 i/o 17 nc i/o 65 56 i/o nc 99 i/o 161 138 i/o 210 181 i/o 18 15 i/o 66 nc i/o 112 100 i/o 162 139 i/o 211 182 gnd 19 16 i/o 67 57 i/o 113 nc i/o 163 140 i/o 212 nc vcc 20 17 i/o 68 58 i/o 114 101 i/o 164 141 i/o 213 183 i/o 21 18 i/o 69 59 gnd 115 nc i/o 165 142 i/o 214 184 i/o 22 19 i/o 70 60 i/o 116 102 i/o 166 nc i/o 215 185 i/o 23 20 i/o 71 61 vcc 117 nc i/o 167 143 i/o 216 186 i/o 24 nc i/o 72 62 i/o 118 nc i/o 168 144 i/o 217 187 vccio 25 21 i/o 73 63 i/o 119 103 trstb 169 145 vcc 218 188 i/o 26 22 i/o 74 64 i/o 120 104 tms 170 nc i/o 219 nc i/o 27 23 gnd 75 nc i/o 121 105 i/o 171 146 i/o 220 189 i/o 28 24 i/o 76 65 i/o 122 nc i/o 172 147 gnd 221 190 i/o 29 25 gclk/i 77 66 i/o 123 106 i/o 173 148 i/o 222 191 i/o 30 26 aclk/i 78 67 i/o 124 107 i/o 174 149 i/o 223 192 i/o 31 27 vcc 79 nc i/o 125 108 i/o 175 150 i/o 224 193 i/o 32 28 gclk/i 80 68 i/o 126 109 i/o 176 151 i/o 225 194 i/o 33 29 gclk/i 81 69 i/o 127 nc i/o 177 152 i/o 226 nc i/o 34 30 vcc 82 70 i/o 128 110 i/o 178 153 i/o 227 195 i/o 35 31 i/o 83 nc i/o 129 111 i/o 179 154 i/o 228 196 i/o 36 32 i/o nc 71 i/o 130 112 i/o 180 155 i/o 229 197 i/o 37 nc gnd 84 nc i/o 131 113 i/o nc 156 i/o 230 198 i/o 38 33 i/o 85 72 i/o 132 114 vcc 181 157 tck 231 nc i/o 39 nc i/o 86 73 gnd 133 115 i/o 182 158 stm 232 199 gnd 40 34 i/o 87 74 i/o 134 116 gnd 183 nc i/o 233 200 i/o 41 35 i/o 88 nc vcc 135 117 i/o 184 159 i/o 234 201 vcc 42 36 i/o 89 75 i/o 136 nc i/o 185 160 i/o 235 202 i/o 43 nc i/o 90 76 i/o 137 118 i/o 186 161 i/o 236 203 i/o 44 37 i/o 91 77 i/o 138 119 i/o 187 162 i/o 237 204 i/o 45 38 i/o 92 78 gnd 139 120 i/o 188 163 gnd 238 205 i/o 46 39 i/o 93 79 i/o 140 121 i/o 189 164 i/o 239 206 i/o 47 nc i/o 94 80 i/o 141 nc i/o 190 165 vcc 240 207 tdo 48 40 i/o 95 81 i/o 142 122 i/o 191 166 i/o 49 41 vcc 96 82 i/o 143 123 i/o 192 nc i/o 50 42 i/o 97 83 vccio 144 124 i/o 193 167 i/o pqfp 208/240 p inout t able
6-59 ql4090 - quickram tm pinout diagram 456 pin pbga top bottom p inout d iagram ql4090-1pb456c quickram pin a1 corner
60 preliminary ql4090 - quickram tm 6-60 pbga 456 pinout table note: nc pins must be left unconnected on printed circuit board pbga 456 p inout t able 456 function 456 function 456 function 456 function 456 function a1 i/o b26 stm d25 i/o h4 i/o m14 gnd/therm a2 i/o c1 i/o d26 i/o h5 nc m15 gnd/therm a3 i/o c2 i/o e1 i/o h22 nc m16 gnd/therm a4 i/o c3 i/o e2 i/o h23 i/o m22 nc a5 i/o c4 tdo e3 i/o h24 i/o m23 nc a6 i/o c5 i/o e4 i/o h25 i/o m24 i/o a7 i/o c6 i/o e5 gnd h26 i/o m25 i/o a8 i/o c7 i/o e6 vcc j1 i/o m26 i/o a9 i/o c8 i/o e7 gnd j2 i/o n1 gclk/i a10 i/o c9 i/o e8 nc j3 i/o n2 i/o a11 i/o c10 i/o e9 gnd j4 nc n3 i/o a12 vccio c11 i/o e10 i/o j5 gnd n4 gclk/i a13 i/o c12 i/o e11 gnd j22 nc n5 vcc a14 i/o c13 i/o e12 gnd j23 nc n11 gnd/therm a15 i/o c14 i/o e13 vcc j24 i/o n12 gnd/therm a16 i/o c15 i/o e14 gnd j25 i/o n13 gnd/therm a17 i/o c16 i/o e15 gnd j26 i/o n14 gnd/therm a18 i/o c17 i/o e16 gnd k1 i/o n15 gnd/therm a19 i/o c18 i/o e17 nc k2 i/o n16 gnd/therm a20 i/o c19 i/o e18 gnd k3 i/o n22 gnd a21 i/o c20 i/o e19 nc k4 i/o n23 i/o a22 i/o c21 i/o e20 gnd k5 vcc n24 i/o a23 i/o c22 i/o e21 vcc k22 gnd n25 i/o a24 i/o c23 i/o e22 gnd k23 i/o n26 i/o a25 i/o c24 i/o e23 i/o k24 i/o p1 i/o a26 i/o c25 tck e24 i/o k25 i/o p2 i/o b1 i/o c26 i/o e25 i/o k26 i/o p3 i/o b2 i/o d1 i/o e26 i/o l1 i/o p4 i/o b3 i/o d2 i/o f1 i/o l2 i/o p5 nc b4 i/o d3 i/o f2 i/o l3 i/o p11 gnd/therm b5 i/o d4 gnd f3 i/o l4 i/o p12 gnd/therm b6 i/o d5 i/o f4 nc l5 nc p13 gnd/therm b7 i/o d6 nc f5 vcc l11 gnd/therm p14 gnd/therm b8 i/o d7 i/o f22 vcc l12 gnd/therm p15 gnd/therm b9 i/o d8 i/o f23 nc l13 gnd/therm p16 gnd/therm b10 i/o d9 gnd f24 i/o l14 gnd/therm p22 nc b11 i/o d10 i/o f25 i/o l15 gnd/therm p23 gclk / i b12 i/o d11 i/o f26 i/o l16 gnd/therm p24 gclk / i b13 i/o d12 gnd g1 i/o l22 nc p25 i/o b14 i/o d13 i/o g2 i/o l23 i/o p26 aclk / i b15 i/o d14 i/o g3 i/o l24 i/o r1 i/o b16 i/o d15 gnd g4 i/o l25 i/o r2 i/o b17 i/o d16 i/o g5 nc l26 i/o r3 i/o b18 i/o d17 i/o g22 gnd m1 aclk / i r4 nc b19 i/o d18 gnd g23 i/o m2 gclk/i r5 nc b20 i/o d19 i/o g24 i/o m3 i/o r11 gnd/therm b21 i/o d20 i/o g25 i/o m4 nc r12 gnd/therm b22 i/o d21 nc g26 i/o m5 gnd r13 gnd/therm b23 i/o d22 i/o h1 i/o m11 gnd/therm r14 gnd/therm b24 i/o d23 gnd h2 i/o m12 gnd/therm r15 gnd/therm b25 i/o d24 i/o h3 i/o m13 gnd/therm r16 gnd/therm (continued next page)
6-61 ql4090 - quickram tm pbga 456 pinout table (continued from previous page) note: nc pins must be left unconnected on printed circuit board 456 function 456 function 456 function 456 function r22 vcc y1 i/o ac6 nc ae5 i/o r23 nc y2 i/o ac7 i/o ae6 i/o r24 i/o y3 i/o ac8 i/o ae7 i/o r25 i/o y4 i/o ac9 nc ae8 i/o r26 gclk / i y5 i/o ac10 i/o ae9 i/o t1 i/o y22gndac11i/oae10i/o t2 i/o y23 i/o ac12 nc ae11 i/o t3 i/o y24 i/o ac13 i/o ae12 i/o t4 i/o y25 i/o ac14 vccio ae13 i/o t5 vcc y26 i/o ac15 nc ae14 i/o t11 gnd/thermal aa1 i/o ac16 i/o ae15 i/o t12 gnd/thermal aa2 i/o ac17 i/o ae16 i/o t13 gnd/thermal aa3 nc ac18 nc ae17 i/o t14 gnd/thermal aa4 nc ac19 i/o ae18 i/o t15 gnd/thermal aa5 vcc ac20 i/o ae19 i/o t16 gnd/thermal aa22 vcc ac21 i/o ae20 i/o t22 gnd aa23 nc ac22 nc ae21 i/o t23 i/o aa24 i/o ac23 gnd ae22 i/o t24 i/o aa25 i/o ac24 i/o ae23 nc t25 i/o aa26 i/o ac25 i/o ae24 tms t26 i/o ab1 i/o ac26 i/o ae25 i/o u1 i/o ab2 i/o ad1 i/o ae26 i/o u2 i/o ab3 i/o ad2 nc af1 i/o u3 i/o ab4 i/o ad3 i/o af2 i/o u4 i/o ab5 gnd ad4 i/o af3 i/o u5 gnd ab6 vcc ad5 i/o af4 i/o u22 nc ab7 nc ad6 i/o af5 i/o u23 i/o ab8 nc ad7 i/o af6 i/o u24 i/o ab9 nc ad8 i/o af7 i/o u25 i/o ab10 vcc ad9 i/o af8 i/o u26 i/o ab11 gnd ad10 i/o af9 i/o v1 i/o ab12 nc ad11 i/o af10 i/o v2 i/o ab13 i/o ad12 i/o af11 i/o v3 i/o ab14 gnd ad13 i/o af12 i/o v4 nc ab15 vcc ad14 i/o af13 i/o v5 nc ab16 i/o ad15 i/o af14 i/o v22 gnd ab17 nc ad16 i/o af15 i/o v23 nc ab18 vcc ad17 i/o af16 i/o v24 i/o ab19 gnd ad18 i/o af17 i/o v25 i/o ab20 nc ad19 i/o af18 i/o v26 i/o ab21 vcc ad20 i/o af19 i/o w1 i/o ab22 gnd ad21 i/o af20 i/o w2 i/o ab23 i/o ad22 i/o af21 i/o w3 i/o ab24 i/o ad23 trstb af22 i/o w4 i/o ab25 i/o ad24 i/o af23 i/o w5 nc ab26 i/o ad25 i/o af24 i/o w22 nc ac1 i/o ad26 i/o af25 i/o w23 i/o ac2 i/o ae1 tdi af26 i/o w24 i/o ac3 nc ae2 i/o w25 i/o ac4 gnd ae3 i/o w26 i/o ac5 i/o ae4 i/o
62 preliminary ql4090 - quickram tm 6-62 pin description ordering information p in d escription pin function description tdi/rsi test data in for jtag / ram init. serial data in hold high during normal operation. connects to serial prom data in for ram initialization. connect to vcc if unused. trstb/rro active low reset for jtag / ram init. reset out hold low during normal operation. connects to serial prom reset for ram initialization. connect to gnd if unused. tms test mode select for jtag hold high during normal operation. connect to vcc if not used for jtag. tck test clock for jtag hold high or low during normal operation. connect to vcc or ground if not used for jtag. tdo/rco test data out for jtag / ram init. clock out connect to serial prom clock for ram initialization. must be left unconnected if not used for jtag or ram initialization. stm special test mode must be grounded during normal operation. i/aclk high-drive input and/or array network driver can be configured as either or both. i/gclk high-drive input and/or global network driver can be configured as either or both. i high-drive input use for input signals with high fanout. i/o input/output pin can be configured as an input and/or output. vcc power supply pin connect to 3.3v supply. vccio input voltage tolerance pin connect to 5.0 volt supply if 5 volt input tolerance is required, otherwise connect to 3.3v supply. gnd ground pin connect to ground. gnd/therm ground/thermal pin available on 456-pbga only. connect to ground plane on pcb if heat sinking desired. otherwise may be left unconnected. ql 4090 - 1 pq208 c operating range c = commercial i = industrial m = military package code pq208 = 208-pin pqfp cf208 = 208-pin cqfp pq240 = 240-pin pqfp pb456 = 456-pin pbga quicklogic device quickram device part number speed grade 0 = quick 1 = fast 2 = faster 3 = faster *4 = wow * contact quicklogic regarding availability.
6-63 ql4090 - quickram tm absolute maximum ratings vcc voltage.......................................-0.5 to 4.6v vccio voltage ...................................-0.5 to 7.0v input voltage ......................... -0.5 to vccio+0.5v latch-up immunity .................................. 200 ma dc input current.................................. 20 ma esd pad protection .............................. 2000v storage temperature .............. -65 c to +150 c lead temperature ........................... .......300 c operating range dc characteristics notes: [1] applies only to -1/-2/-3/-4 commercial grade devices. these speed grades are also pci-compliant. all other devices have 8 ma iol specifications. [2]capacitance is sample tested only. clock pins are 12 pf maximum. [3]only one output at a time. duration should not exceed 30 seconds. [4]for -1/-2/-3/-4 commercial grade devices only. maximum icc is 3 ma for -0 commercial grade and all industrial grade devices, and 5 ma for all military grade devices. for ac conditions, contact quicklogic customer engineering. symbol parameter military industrial commercial unit min max min max min max vcc supply voltage 3.0 3.6 3.0 3.6 3.0 3.6 v vccio i/o input tolerance voltage 3.0 5.5 3.0 5.5 3.0 5.25 v ta ambient temperature -55 -40 85 0 70 c tc case temperature 125 c -0 speed grade 0.42 2.03 0.43 1.90 0.46 1.85 k delay factor -1 speed grade 0.42 1.64 0.43 1.54 0.46 1.50 -2 speed grade 0.42 1.37 0.43 1.28 0.46 1.25 -3 speed grade n/a n/a 0.43 0.90 0.46 0.88 -4 speed grade n/a n/a 0.43 0.82 0.46 0.80 symbol parameter conditions min max unit vih input high voltage 0.5vcc vccio+0.5 v vil input low voltage -0.5 0.3vcc v voh output high voltage ioh = -12 ma 2.4 v ioh = -500 a 0.9vcc v vol output low voltage iol = 16 ma [1] 0.45 v iol = 1.5 ma 0.1vcc v ii i or i/o input leakage current vi = vccio or gnd -10 10 a ioz 3-state output leakage current vi = vccio or gnd -10 10 a ci input capacitance [2] 10 pf ios output short circuit current [3] vo = gnd -15 -180 ma vo = vcc 40 210 ma icc d.c. supply current [4] vi, vio = vccio or gnd 0.50 (typ) 2 ma iccio d.c. supply current on vccio 0 100 a
64 preliminary ql4090 - quickram tm 6-64 ac characteristics at vcc = 3.3v, ta = 25 c (k = 1.00) (to calculate delays, multiply the appropriate k factor in the "operating range" section by the following numbers.) logic cells ram cell synchronous write timing notes: [5]stated timing for worst case propagation delay over process variation at vcc=3.3v and ta=25 c. multiply by the appropriate delay factor, k, for speed grade, voltage and temperature settings as specified in the operating range. [6]these limits are derived from a representative selection of the slowest paths through the quickram logic cell including typical net delays. worst case delay values for specific paths should be determined from timing anal- ysis of your particular design. symbol parameter propagation delays (ns) fanout [5] 12348 tpd combinatorial delay [6] 1.4 1.7 1.9 2.2 3.2 tsu setup time [6] 1.7 1.7 1.7 1.7 1.7 th hold time 0.0 0.0 0.0 0.0 0.0 tclk clock to q delay 0.7 1.0 1.2 1.5 2.5 tcwhi clock high time 1.2 1.2 1.2 1.2 1.2 tcwlo clock low time 1.2 1.2 1.2 1.2 1.2 tset set delay 1.0 1.3 1.5 1.8 2.8 treset reset delay 0.8 1.1 1.3 1.6 2.6 tsw set width 1.9 1.9 1.9 1.9 1.9 trw reset width 1.8 1.8 1.8 1.8 1.8 symbol parameter propagation delays (ns) fanout 12348 tswa wa setup time to wclk 1.0 1.0 1.0 1.0 1.0 thwa wa hold time to wclk 0.0 0.0 0.0 0.0 0.0 tswd wd setup time to wclk 1.0 1.0 1.0 1.0 1.0 thwd wd hold time to wclk 0.0 0.0 0.0 0.0 0.0 tswe we setup time to wclk 1.0 1.0 1.0 1.0 1.0 thwe we hold time to wclk 0.0 0.0 0.0 0.0 0.0 twcrd wclk to rd (wa=ra) [5] 5.0 5.3 5.6 5.9 7.1
6-65 ql4090 - quickram tm ram cell synchronous read timing ram cell asynchronous read timing input-only/clock cells clock cells notes: [7]the array distributed networks consist of 40 half columns and the global distributed networks consist of 44 half columns, each driven by an independent buffer. the number of half columns used does not affect clock buffer delay. the array clock has up to 8 loads per half column. the global clock has up to 11 loads per half column. symbol parameter propagation delays (ns) fanout 12348 tsra ra setup time to rclk 1.0 1.0 1.0 1.0 1.0 thra ra hold time to rclk 0.0 0.0 0.0 0.0 0.0 tsre re setup time to rclk 1.0 1.0 1.0 1.0 1.0 thre re hold time to rclk 0.0 0.0 0.0 0.0 0.0 trcrd rclk to rd [5] 4.0 4.3 4.6 4.9 6.1 symbol parameter propagation delays (ns) fanout 12348 rpdrd ra to rd [5] 3.0 3.3 3.6 3.9 5.1 symbol parameter propagation delays (ns) fanout [5] 123481224 tin high drive input delay 1.5 1.6 1.8 1.9 2.4 2.9 4.4 tini high drive input, inverting delay 1.6 1.7 1.9 2.0 2.5 3.0 4.5 tisu input register set-up time 3.1 3.1 3.1 3.1 3.1 3.1 3.1 tih input register hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 tlclk input register clock to q 0.7 0.8 1.0 1.1 1.6 2.1 3.6 tlrst input register reset delay 0.6 0.7 0.9 1.0 1.5 2.0 3.5 tlesu input register clock enable setup time 2.3 2.3 2.3 2.3 2.3 2.3 2.3 tleh input register clock enable hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 symbol parameter propagation delays (ns) loads per half column [7] 123481011 tack array clock delay 1.2 1.2 1.3 1.3 1.5 1.6 1.7 tgckp global clock pin delay 0.7 0.7 0.7 0.7 0.7 0.7 0.7 tgckb global clock buffer delay 0.8 0.8 0.9 0.9 1.1 1.2 1.3
66 preliminary ql4090 - quickram tm 6-66 i/o cell input delays i/o cell output delays notes: [8]the following loads are used for tpxz symbol parameter propagation delays (ns) fanout [5] 1234810 ti/o input delay (bidirectional pad) 1.3 1.6 1.8 2.1 3.1 3.6 tisu input register set-up time 3.1 3.1 3.1 3.1 3.1 3.1 tih input register hold time 0.0 0.0 0.0 0.0 0.0 0.0 tloclk input register clock to q 0.7 1.0 1.2 1.5 2.5 3.0 tlorst input register reset delay 0.6 0.9 1.1 1.4 2.4 2.9 tlesu input register clock enable set-up time 2.3 2.3 2.3 2.3 2.3 2.3 tleh input register clock enable hold time 0.0 0.0 0.0 0.0 0.0 0.0 symbol parameter propagation delays (ns) output load capacitance (pf) 30 50 75 100 150 toutlh output delay low to high 2.1 2.5 3.1 3.6 4.7 touthl output delay high to low 2.2 2.6 3.2 3.7 4.8 tpzh output delay tri-state to high 1.2 1.7 2.2 2.8 3.9 tpzl output delay tri-state to low 1.6 2.0 2.6 3.1 4.2 tphz output delay high to tri-state [8] 2.0 tplz output delay low to tri-state [8] 1.2 5 pf 1k ? 5 pf 1k ? tphz tplz

▲Up To Search▲

Price & Availability of QL4090-0PQ208C

	To Download QL4090-0PQ208C Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .